Design and Comparative analysis of Mux Tree using Different Low Power Design Techniques

The work present in this paper depicts the design and thorough comparative analysis of a digital circuit namely, 4X1 mux tree (data selector) using different Low Power design techniques i.e., Standard body bias technique, DTMOS, FGMOS, Quasi-FGMOS(QFGMOS). Ultra-Low power, High Speed and Low voltage is the need of the hour in the VLSI industry. So, this paper further investigates the performance characteristics and scrutiny of each technique described above to ensure the tradeoff between various parameters in best possible way as per the requirement. The simulations in the proposed paper are carried out in LTSPICE using TSMC 180nm technology by keeping all the design parameters such as aspect ratio, input voltage, bias voltage same. Power dissipated, Output voltage, delay, PDP and EDP are also calculated for each technique based circuitry.