Data-flow implementation of concurrent asynchronous systems

Embedded multi core systems are implemented as systems-on-chip (SoC) that rely on packet store-and-forward networks-on-chip (NoC) for communications. These systems do not use busses nor global clock. Instead routers are used to move data between the cores and each core uses its own local clock. This implies concurrent asynchronous computing. Implementing algorithms in such system is very much facilitated using event-driven concepts. In this work, we propose an event-driven hardware computational model that is more suitable to describe, simulate, and design concurrent asynchronous systems. The proposed model of computation has advantages such as flexible I/O timing in term of scheduling policy, processing wise execute as soon as possible, and self timed event driven system. In other words, I/O timing and correctness of algorithm evaluation are dissociated in this work. The main advantage of this proposal is ability to obfuscate algorithm evaluation to thwart side-channel attacks which has important implications for cryptographic applications.