{"title":"无掺杂CMOS电可重构双金属栅平面场效应晶体管的制备与仿真","authors":"Tillmann A. Krauss, Frank Wessely, U. Schwalke","doi":"10.1109/DTIS.2017.7930155","DOIUrl":null,"url":null,"abstract":"In this paper, we illustrate by simulation and extend our previous work by demonstration of fabricated devices of electrostatically doped, reconfigurable planar field-effect-transistors with dual work function metal gates. The technological cornerstones for this dual-gated general purpose FET contain Schottky S/D junctions on a silicon-on-insulator substrate. The transistor type, i.e. n-type or p-type FET, is electrically selectable in operation by applying a control-gate voltage which significantly increases the versatility and flexibility in the design of digital integrated circuits.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Fabrication and simulation of electrically reconfigurable dual metal-gate planar field-effect transistors for dopant-free CMOS\",\"authors\":\"Tillmann A. Krauss, Frank Wessely, U. Schwalke\",\"doi\":\"10.1109/DTIS.2017.7930155\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we illustrate by simulation and extend our previous work by demonstration of fabricated devices of electrostatically doped, reconfigurable planar field-effect-transistors with dual work function metal gates. The technological cornerstones for this dual-gated general purpose FET contain Schottky S/D junctions on a silicon-on-insulator substrate. The transistor type, i.e. n-type or p-type FET, is electrically selectable in operation by applying a control-gate voltage which significantly increases the versatility and flexibility in the design of digital integrated circuits.\",\"PeriodicalId\":328905,\"journal\":{\"name\":\"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)\",\"volume\":\"39 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-04-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DTIS.2017.7930155\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DTIS.2017.7930155","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Fabrication and simulation of electrically reconfigurable dual metal-gate planar field-effect transistors for dopant-free CMOS
In this paper, we illustrate by simulation and extend our previous work by demonstration of fabricated devices of electrostatically doped, reconfigurable planar field-effect-transistors with dual work function metal gates. The technological cornerstones for this dual-gated general purpose FET contain Schottky S/D junctions on a silicon-on-insulator substrate. The transistor type, i.e. n-type or p-type FET, is electrically selectable in operation by applying a control-gate voltage which significantly increases the versatility and flexibility in the design of digital integrated circuits.