Sh-BOOM: the sound of the RISC market changing

ABsmAcP RISC CPUS have been having a hard time jinding their market niche due to high system costs. ShBOOM was designed as a highpe~onnance 50 A4hz 32-bit stack-based RISC CPU with a minimal system cost. By being more reduced than other RISC processors, CPU cost has been minimized. Incoqvorating system support functions within the CPU, such as DMA processor, also reduces the system cost and reduces complexity. Eight-bit instructions within 32-bit words supplies a 4-byte instruction cache at minimal expense. On-board DRAM control and refresh allows maintaining two banks in fast page-mode without external circuitry. A highly multiplexed bus lweps package size down (44 pin PLCC) and minimalist design keeps the silicon small (WM gates) resulting in a chip that should sell for a Jactor of jive to ten less than other processors of comparable power. A substantially complete prototype of the processor has been built and fimctions as designed.