{"title":"一个3mW 12b 10MS/s子范围SAR ADC","authors":"Hung-Wei Chen, Yu-Hsun Liu, Yu-Hsiang Lin, Hsin-Shu Chen","doi":"10.1109/ASSCC.2009.5357201","DOIUrl":null,"url":null,"abstract":"This paper presents a successive approximation analog-to-digital converter (SAR ADC) achieving high power efficiency by adopting sub-range concept. Overlapping range greatly relieves the accuracy requirement on the first 6 bit resolving in coarse conversion. The error made in the coarse conversion is recovered during the rest 7 bit resolving in fine conversion. Hence, it significantly reduces the capacitor array output settling time of most-significant-bit (MSB) capacitor switching, which is the speed bottleneck for traditional SAR ADC. A 3mW 12b 10MS/s sub-range SAR ADC is realized in 0.13-μm CMOS process. The prototype circuit reaches SNDR 59.7dB at Nyquist input frequency. It occupies an active chip area of 0.096 mm2.","PeriodicalId":263023,"journal":{"name":"2009 IEEE Asian Solid-State Circuits Conference","volume":"357 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-12-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"A 3mW 12b 10MS/s sub-range SAR ADC\",\"authors\":\"Hung-Wei Chen, Yu-Hsun Liu, Yu-Hsiang Lin, Hsin-Shu Chen\",\"doi\":\"10.1109/ASSCC.2009.5357201\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a successive approximation analog-to-digital converter (SAR ADC) achieving high power efficiency by adopting sub-range concept. Overlapping range greatly relieves the accuracy requirement on the first 6 bit resolving in coarse conversion. The error made in the coarse conversion is recovered during the rest 7 bit resolving in fine conversion. Hence, it significantly reduces the capacitor array output settling time of most-significant-bit (MSB) capacitor switching, which is the speed bottleneck for traditional SAR ADC. A 3mW 12b 10MS/s sub-range SAR ADC is realized in 0.13-μm CMOS process. The prototype circuit reaches SNDR 59.7dB at Nyquist input frequency. It occupies an active chip area of 0.096 mm2.\",\"PeriodicalId\":263023,\"journal\":{\"name\":\"2009 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"357 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-12-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2009.5357201\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2009.5357201","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents a successive approximation analog-to-digital converter (SAR ADC) achieving high power efficiency by adopting sub-range concept. Overlapping range greatly relieves the accuracy requirement on the first 6 bit resolving in coarse conversion. The error made in the coarse conversion is recovered during the rest 7 bit resolving in fine conversion. Hence, it significantly reduces the capacitor array output settling time of most-significant-bit (MSB) capacitor switching, which is the speed bottleneck for traditional SAR ADC. A 3mW 12b 10MS/s sub-range SAR ADC is realized in 0.13-μm CMOS process. The prototype circuit reaches SNDR 59.7dB at Nyquist input frequency. It occupies an active chip area of 0.096 mm2.
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