{"title":"70 ghz有效采样率时域数字化片上示波器","authors":"M. Safi-Harb, G. Roberts","doi":"10.1109/CICC.2006.320964","DOIUrl":null,"url":null,"abstract":"An on-chip digitizer for the transient measurement of digital signal integrity is proposed. Undersampling, combined with single-path time-domain processing is used to perform the embedded measurement in a time-efficient manner. On-chip interconnect crosstalk generation with variable strength is included on chip for characterization, and successfully measured using a prototype chip, implemented in a 0.18 mum CMOS process. The proposed system is easily calibratable, with an estimated static power dissipation of ~3.5 mW. The total active area taken up by the associated test and calibration vehicles is 0.45 mm2","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 70-GHz Effective Sampling Rate On-Chip Oscilloscope with Time-Domain Digitization\",\"authors\":\"M. Safi-Harb, G. Roberts\",\"doi\":\"10.1109/CICC.2006.320964\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An on-chip digitizer for the transient measurement of digital signal integrity is proposed. Undersampling, combined with single-path time-domain processing is used to perform the embedded measurement in a time-efficient manner. On-chip interconnect crosstalk generation with variable strength is included on chip for characterization, and successfully measured using a prototype chip, implemented in a 0.18 mum CMOS process. The proposed system is easily calibratable, with an estimated static power dissipation of ~3.5 mW. The total active area taken up by the associated test and calibration vehicles is 0.45 mm2\",\"PeriodicalId\":269854,\"journal\":{\"name\":\"IEEE Custom Integrated Circuits Conference 2006\",\"volume\":\"38 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Custom Integrated Circuits Conference 2006\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2006.320964\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Custom Integrated Circuits Conference 2006","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2006.320964","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
提出了一种用于数字信号完整性瞬态测量的片上数字化仪。欠采样与单路径时域处理相结合,以时间效率的方式进行嵌入式测量。具有可变强度的片上互连串扰生成包括在芯片上进行表征,并使用原型芯片成功测量,在0.18 μ m CMOS工艺中实现。该系统易于校准,估计静态功耗约为3.5 mW。相关测试及校正车辆占用的总活动面积为0.45 mm2
A 70-GHz Effective Sampling Rate On-Chip Oscilloscope with Time-Domain Digitization
An on-chip digitizer for the transient measurement of digital signal integrity is proposed. Undersampling, combined with single-path time-domain processing is used to perform the embedded measurement in a time-efficient manner. On-chip interconnect crosstalk generation with variable strength is included on chip for characterization, and successfully measured using a prototype chip, implemented in a 0.18 mum CMOS process. The proposed system is easily calibratable, with an estimated static power dissipation of ~3.5 mW. The total active area taken up by the associated test and calibration vehicles is 0.45 mm2