优化SiCOH介电体集成在90nm CMOS技术

A. Grill, D. Edelstein, D. Restaino, M. Lane, S. Gates, E. Liniger, T. Shaw, X. Liu, D. Klaus, V. Patel, S. Cohen, E. Simonyi, N. Klymko, S. Lane, K. Ida, S. Vogt, T. Van Kleeck, C. Davis, M. Ono, T. Nogami, T. Ivers
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引用次数: 9

摘要

将SiCOH薄膜集成到可靠的ULSI集成电路芯片中,对介质材料的性能提出了许多要求。本文介绍了在90nm工艺节点中,选择集成在ULSI CMOS芯片Cu布线级的最佳薄膜的选择和优化过程。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Optimization of SiCOH dielectrics for integration in a 90nm CMOS technology
The research integration of SiCOH films in a reliable ULSI integrated circuit chip imposes many requirements on the properties of the dielectric material. This paper describes a selection and optimization process for choosing the best film to be integrated in Cu wiring levels of ULSI CMOS chips in the 90 nm technology node.
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