容错电路和概率检验证明

A. Gál, M. Szegedy
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引用次数: 16

摘要

提出了一种新的布尔电路容错模型。我们考虑同步电路,我们允许对手在电路的每一级选择一个小的恒定分数的门是错误的。我们要求,即使在存在这种故障的情况下,电路也要计算给定函数的“松散版本”。我们证明了在这个模型中,每个对称函数都有一个小的(大小为O(n),深度为O(log n))容错电路。我们还展示了我们的模型和概率可检验证明之间可能意想不到的关系。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Fault tolerant circuits and probabilistically checkable proofs
We introduce a new model of fault tolerance for Boolean circuits. We consider synchronized circuits and we allow an adversary to choose a small constant fraction of the gates at each level of the circuit to be faulty. We require that even in the presence of such faults the circuit compute a "loose version" of the given function. We show that every symmetric function has a small (size O(n), depth O(log n)) fault tolerant circuit in this model. We also show a perhaps unexpected relation between our model and probabilistically checkable proofs.
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