Using the stuck-at fault model: how well does it work?

Many researchers have studied methods for both gen­ erating and simulating faults in CMOS chips. A good deal of focus has been on gate level modeling and test generation methods. The stuck at fault model and various derivations of it are still most widely used to generate test sets. Other researchers have demon­ strated the inappropriateness of the stuck at fault model for generating effective test sets for CMOS cir­ cuits. Among the fault types often missed are tran­ sistor faults, bridging faults and delay faults. In this paper a set of experiments are described to measure the effectiveness of gate level test generation methods on transistor faults. 1 I n t r o d u c t io n With the increasing densities of transistors being built onto single CMOS chips, the problem of detecting a faulty chip becomes more difficult, and the probabil­ ity of a faulty chip passing tests increases. Provided that the design phase of chip development is fault free, faults in a CMOS chip are the result of errors that oc­ cur in the fabrication process. These errors include extra or missing material on one or more of the lay­ ers built during fabrication. Researchers have studied the effects of these defects on circuit performance and classified them into different fault types[l]. 1 .1 T h e G a t e L e v e l M o d e l a n d T e s t in g Traditionally, tests for faults in the combinational por­ tion of a chip have been generated using the single line (node) stuck at fault model[2]. In this model, inputs and outputs of each logic gate (and, nand, inverter, etc.) are stimulated to produce the desired good out*This work wai supported by a grant from the Microelec­ tronics Center of North Carolina Permission to copy without fee all or part of this material is granted provided that the copies are not made or distributed for direct com­ mercial advantage, the ACM copyright notice and the title of the publication and its date appear, and notice Is given that copying Is by permission of the Association for Computing Machinery. To copy otherwise, or to republish, requires a fee and/or specific per­ mission. ©1990 ACM 0-89791-356-6/90/0400/0040 $1.50 put. In the faulty circuit, the value of a single input or output node is replaced with a logic value differ­ ent from the good circuit, thus indicating the stuck-at fault. The output of the faulty gate must then have the opposite logic value from the good circuit output to indicate the fault. For example, a three input nand gate has 8 stuck at faults in this model (see figurel). They are inputs, a, 6, and c, stuck at logic O(aaO) and stuck at logic l(sa /), and the output, z, stuck at 1 and stuck at 0. It is easy to see that if any of the inputs are stuck at 0, the output will always be a logic 1. Therefore, these faults, a sa0,b saO, c taO and z sal, fall into the same equivalence class and can all be detected by the same test: apply logic 1 to all inputs and observe a 0 on the output. If any of these faults are present, the output will be different (logic 1) from the good circuit (logic 0). The fault equivalence is not main­ tained when we reverse the logic values on the inputs and outputs, however. If input a sal, then to observe a difference on the output z we must apply, b—1, c=l, a=0, and observe output z=0 in the faulty gate; z=l in the unfaulty gate. Each of the inputs a, b, and c, must be tested individually; however a test for any in­ put sal will also detect output z saO. So, a total of four test vectors are needed to cover all the faults in the gate level model of a three input nand gate. We can apply the fault equivalence property to other gates in the circuit as well. In general, the tests needed to cover the faults for a particular gate may also cover the faults of other gates in that circuit. Using this in­ formation, equivalence fault collapsing is performed to determine a smaller number of faults that need to be covered in order to detect all the gate level faults in the circuit. When individual gates are connected together, test generation becomes more complicated. One cannot control directly the input to an embedded gate, nor can one observe directly the output of such a gate. So, testing a gate for faults involves stimulation of logic values on the input nodes (via outputs of gates occur­ ring before the gate in test) and propagation of the output node’s value (via gates occurring after the gale in test) to a circuit output. Various methods have been