一种用于快速行周期DRAM的VPM(虚拟流水线内存)架构

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1999-08-23 DOI:10.1109/APASIC.1999.824115

Chi-Weon Yoon, Yon-Kyun Im, Seon‐Ho Han, H. Yoo, T. Jung

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引用次数: 2

摘要

采用自顶向下的设计方法，提出了一种快速行周期的虚拟流水线内存(VPM)体系结构。行路径中的管道结构和多个SRAM缓冲区的集成实现了快速的行周期。VPM的性能比SDRAM高出约40%，比VCM高出约20%。VPM保持了与传统SDRAM接口的向后兼容性，并通过采用部分cell core激活来降低功耗。

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A VPM (Virtual Pipelined Memory) architecture for a fast row-cycle DRAM

We propose a Virtual Pipelined Memory (VPM) architecture for fast row-cycle by using a top-down design approach. A pipeline structure in the row path and integration of multiple SRAM buffers enable fast row-cycle. VPM shows higher performance than that of SDRAM by about 40% and that of VCM by about 20%. VPM maintains backward compatibility with a conventional SDRAM interface and consumes low power by adopting partial cell core activation.

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来源期刊

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

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