{"title":"高吞吐量递归系统卷积编码器的设计优化","authors":"Luca Pilato, Gabriele Meoni, L. Fanucci","doi":"10.1109/ICSTCC.2018.8540693","DOIUrl":null,"url":null,"abstract":"Recursive Systematic Convolutional (RSC) codes are the building blocks of the modern communication systems. In this paper we propose a new analytical model to manipulate the modulo-2 algebraic operations and a finite state machine model describing the single-cycle RSC architecture to design high throughput RSC code with special emphasis for parallel implementation and a puncturing scheme embedded in the design. The new design approach is suitable for any RSC code and for almost any degree of parallelism implementations. We also present some case studies about the RSC code architecture and some simulation results for the Bit Error Rate, to compare commonly used RSC codes with different constraints on the length, and redesigned with the proposed methodology.","PeriodicalId":308427,"journal":{"name":"2018 22nd International Conference on System Theory, Control and Computing (ICSTCC)","volume":"35 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design Optimization for High Throughput Recursive Systematic Convolutional Encoders\",\"authors\":\"Luca Pilato, Gabriele Meoni, L. Fanucci\",\"doi\":\"10.1109/ICSTCC.2018.8540693\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Recursive Systematic Convolutional (RSC) codes are the building blocks of the modern communication systems. In this paper we propose a new analytical model to manipulate the modulo-2 algebraic operations and a finite state machine model describing the single-cycle RSC architecture to design high throughput RSC code with special emphasis for parallel implementation and a puncturing scheme embedded in the design. The new design approach is suitable for any RSC code and for almost any degree of parallelism implementations. We also present some case studies about the RSC code architecture and some simulation results for the Bit Error Rate, to compare commonly used RSC codes with different constraints on the length, and redesigned with the proposed methodology.\",\"PeriodicalId\":308427,\"journal\":{\"name\":\"2018 22nd International Conference on System Theory, Control and Computing (ICSTCC)\",\"volume\":\"35 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 22nd International Conference on System Theory, Control and Computing (ICSTCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSTCC.2018.8540693\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 22nd International Conference on System Theory, Control and Computing (ICSTCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSTCC.2018.8540693","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design Optimization for High Throughput Recursive Systematic Convolutional Encoders
Recursive Systematic Convolutional (RSC) codes are the building blocks of the modern communication systems. In this paper we propose a new analytical model to manipulate the modulo-2 algebraic operations and a finite state machine model describing the single-cycle RSC architecture to design high throughput RSC code with special emphasis for parallel implementation and a puncturing scheme embedded in the design. The new design approach is suitable for any RSC code and for almost any degree of parallelism implementations. We also present some case studies about the RSC code architecture and some simulation results for the Bit Error Rate, to compare commonly used RSC codes with different constraints on the length, and redesigned with the proposed methodology.