Imtiaj Ahmed, Shafiul Alam, M. A. U. Rahman, Naimul Islam
{"title":"图形算法在可重构硬件(fpga)中的实现以加快执行速度","authors":"Imtiaj Ahmed, Shafiul Alam, M. A. U. Rahman, Naimul Islam","doi":"10.1109/ICCIT.2009.302","DOIUrl":null,"url":null,"abstract":"This paper focus on hardware representation and implementation of graph algorithms in Reconfigurable Hardware (FPGAs) to speeding up the execution. Generally, Software implementations of graph algorithms in high level languages such as C or C++ are lack of speed and efficiency, although they are flexible and cost effective. Moreover, since FPGA is used to implement the algorithms, it can be modify and programmed to the desired application or functionality requirements. Three candidate graph algorithms have been selected for this purpose and their dynamic graph representation, modeling and simulation in VHDL using Cadence and Xilinx design tools have been presented.","PeriodicalId":112416,"journal":{"name":"2009 Fourth International Conference on Computer Sciences and Convergence Information Technology","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Implementation of Graph Algorithms in Reconfigurable Hardware (FPGAs) to Speeding Up the Execution\",\"authors\":\"Imtiaj Ahmed, Shafiul Alam, M. A. U. Rahman, Naimul Islam\",\"doi\":\"10.1109/ICCIT.2009.302\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper focus on hardware representation and implementation of graph algorithms in Reconfigurable Hardware (FPGAs) to speeding up the execution. Generally, Software implementations of graph algorithms in high level languages such as C or C++ are lack of speed and efficiency, although they are flexible and cost effective. Moreover, since FPGA is used to implement the algorithms, it can be modify and programmed to the desired application or functionality requirements. Three candidate graph algorithms have been selected for this purpose and their dynamic graph representation, modeling and simulation in VHDL using Cadence and Xilinx design tools have been presented.\",\"PeriodicalId\":112416,\"journal\":{\"name\":\"2009 Fourth International Conference on Computer Sciences and Convergence Information Technology\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-11-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 Fourth International Conference on Computer Sciences and Convergence Information Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCIT.2009.302\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Fourth International Conference on Computer Sciences and Convergence Information Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCIT.2009.302","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Implementation of Graph Algorithms in Reconfigurable Hardware (FPGAs) to Speeding Up the Execution
This paper focus on hardware representation and implementation of graph algorithms in Reconfigurable Hardware (FPGAs) to speeding up the execution. Generally, Software implementations of graph algorithms in high level languages such as C or C++ are lack of speed and efficiency, although they are flexible and cost effective. Moreover, since FPGA is used to implement the algorithms, it can be modify and programmed to the desired application or functionality requirements. Three candidate graph algorithms have been selected for this purpose and their dynamic graph representation, modeling and simulation in VHDL using Cadence and Xilinx design tools have been presented.