图形算法在可重构硬件(fpga)中的实现以加快执行速度

Imtiaj Ahmed, Shafiul Alam, M. A. U. Rahman, Naimul Islam
{"title":"图形算法在可重构硬件(fpga)中的实现以加快执行速度","authors":"Imtiaj Ahmed, Shafiul Alam, M. A. U. Rahman, Naimul Islam","doi":"10.1109/ICCIT.2009.302","DOIUrl":null,"url":null,"abstract":"This paper focus on hardware representation and implementation of graph algorithms in Reconfigurable Hardware (FPGAs) to speeding up the execution. Generally, Software implementations of graph algorithms in high level languages such as C or C++ are lack of speed and efficiency, although they are flexible and cost effective. Moreover, since FPGA is used to implement the algorithms, it can be modify and programmed to the desired application or functionality requirements. Three candidate graph algorithms have been selected for this purpose and their dynamic graph representation, modeling and simulation in VHDL using Cadence and Xilinx design tools have been presented.","PeriodicalId":112416,"journal":{"name":"2009 Fourth International Conference on Computer Sciences and Convergence Information Technology","volume":"37 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-11-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Implementation of Graph Algorithms in Reconfigurable Hardware (FPGAs) to Speeding Up the Execution\",\"authors\":\"Imtiaj Ahmed, Shafiul Alam, M. A. U. Rahman, Naimul Islam\",\"doi\":\"10.1109/ICCIT.2009.302\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper focus on hardware representation and implementation of graph algorithms in Reconfigurable Hardware (FPGAs) to speeding up the execution. Generally, Software implementations of graph algorithms in high level languages such as C or C++ are lack of speed and efficiency, although they are flexible and cost effective. Moreover, since FPGA is used to implement the algorithms, it can be modify and programmed to the desired application or functionality requirements. Three candidate graph algorithms have been selected for this purpose and their dynamic graph representation, modeling and simulation in VHDL using Cadence and Xilinx design tools have been presented.\",\"PeriodicalId\":112416,\"journal\":{\"name\":\"2009 Fourth International Conference on Computer Sciences and Convergence Information Technology\",\"volume\":\"37 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-11-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 Fourth International Conference on Computer Sciences and Convergence Information Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCIT.2009.302\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 Fourth International Conference on Computer Sciences and Convergence Information Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCIT.2009.302","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

本文重点研究了图形算法在可重构硬件(fpga)中的硬件表示和实现,以加快图形算法的执行速度。一般来说,图形算法的软件实现在高级语言(如C或c++)中缺乏速度和效率,尽管它们是灵活和经济的。此外,由于FPGA用于实现算法,因此可以根据所需的应用或功能需求对其进行修改和编程。为此选择了三种候选图形算法,并利用Cadence和Xilinx设计工具在VHDL中给出了它们的动态图形表示、建模和仿真。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Implementation of Graph Algorithms in Reconfigurable Hardware (FPGAs) to Speeding Up the Execution
This paper focus on hardware representation and implementation of graph algorithms in Reconfigurable Hardware (FPGAs) to speeding up the execution. Generally, Software implementations of graph algorithms in high level languages such as C or C++ are lack of speed and efficiency, although they are flexible and cost effective. Moreover, since FPGA is used to implement the algorithms, it can be modify and programmed to the desired application or functionality requirements. Three candidate graph algorithms have been selected for this purpose and their dynamic graph representation, modeling and simulation in VHDL using Cadence and Xilinx design tools have been presented.
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