Hardware implementation for the interpolation filter in HEVC standard

High-efficiency video coding, as a new generation of multimedia video standard, has doubled the compression ratio and increased the computational complexity by 2–3 times of the same image quality in the previous H.264 video standard. The interpolation filter is one of the most complicated parts of motion estimation. However, meeting the requirements of real-time performance is difficult to realize by using a software. Thus, we propose in this paper an architecture for the interpolation filter that is easy to implement by using a hardware, and this newly designed architecture has high utilization of hardware resources. The design uses QUARTUS II integrated on Altera’s Stratix V series chips. The findings show that the utilization of hardware resources in this study is less than those reported in the existing literature. The maximum operating frequency of the hardware architecture proposed in this paper can reach 420.71 MHz, which supports real-time processing of 4K videos.