An optimal lookahead processor to prune search space

The discrete relaxation algorithm (DRA) is an efficient computational technique for enforcing arc consistency (AC) in a consistent labeling problem (CLP). The original sequential AC-1 algorithm suffers from O(n/sup 3/m/sup 3/) time complexity for an n-object and m-label problem. Sample problem runs show that all these sequential algorithms are too slow to meet the need for any useful real-time CLP applications. An optimal parallel DRA5 algorithm that reaches the optimal lower bound, O(nm), for parallel AC algorithms (where the number of processors is polynomial in the problem size) is given. The algorithm has been implemented on a fine-grained, massively parallel hardware computer architecture. For problems of practical interest, 4 to 10 orders of magnitude of efficiency improvement can be reached on this hardware architecture.<>