{"title":"高速内存高效网络入侵检测系统","authors":"Wei Lin, Xiaofei Wang, Yaxuan Qi, D. Pao, B. Liu","doi":"10.1109/INFCOMW.2009.5072152","DOIUrl":null,"url":null,"abstract":"In this paper, two-stage NIDS architecture is proposed, which aims to both increase the throughput and reduce memory cost. The contributions of this work are listed below.","PeriodicalId":252414,"journal":{"name":"IEEE INFOCOM Workshops 2009","volume":"49 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"High-Speed Memory-Efficient Network Intrusion Detection System\",\"authors\":\"Wei Lin, Xiaofei Wang, Yaxuan Qi, D. Pao, B. Liu\",\"doi\":\"10.1109/INFCOMW.2009.5072152\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, two-stage NIDS architecture is proposed, which aims to both increase the throughput and reduce memory cost. The contributions of this work are listed below.\",\"PeriodicalId\":252414,\"journal\":{\"name\":\"IEEE INFOCOM Workshops 2009\",\"volume\":\"49 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-04-19\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE INFOCOM Workshops 2009\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/INFCOMW.2009.5072152\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE INFOCOM Workshops 2009","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/INFCOMW.2009.5072152","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High-Speed Memory-Efficient Network Intrusion Detection System
In this paper, two-stage NIDS architecture is proposed, which aims to both increase the throughput and reduce memory cost. The contributions of this work are listed below.