{"title":"用于高速串行链路的90nm 1-4.25 gb /s多数据速率接收器","authors":"Lidong Chen, F. Spagna, P. Marzolf, J.K. Wu","doi":"10.1109/ASSCC.2006.357933","DOIUrl":null,"url":null,"abstract":"This paper describes the design of a receiver that supports the operation from 1 to 4.25-Gb/s, enabling a single macro to satisfy different protocols. The receiver performs equalization to compensate for interconnect ISI, achieves 10 mV sensitivity at 4.25-Gb/s by using offset corrected amplification, and performs clock-data-recovery with a digital algorithm that controls a recovered clock out of a phase interpolator. The receiver has been validated in 90 nm CMOS with 45 mW at 1.1 V supply voltage and demonstrated to achieve link over 30-meter AGW24 cable at 3.125 Gb/s with BER<10-5.","PeriodicalId":142478,"journal":{"name":"2006 IEEE Asian Solid-State Circuits Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A 90nm 1-4.25-Gb/s Multi Data Rate Receiver for High Speed Serial Links\",\"authors\":\"Lidong Chen, F. Spagna, P. Marzolf, J.K. Wu\",\"doi\":\"10.1109/ASSCC.2006.357933\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the design of a receiver that supports the operation from 1 to 4.25-Gb/s, enabling a single macro to satisfy different protocols. The receiver performs equalization to compensate for interconnect ISI, achieves 10 mV sensitivity at 4.25-Gb/s by using offset corrected amplification, and performs clock-data-recovery with a digital algorithm that controls a recovered clock out of a phase interpolator. The receiver has been validated in 90 nm CMOS with 45 mW at 1.1 V supply voltage and demonstrated to achieve link over 30-meter AGW24 cable at 3.125 Gb/s with BER<10-5.\",\"PeriodicalId\":142478,\"journal\":{\"name\":\"2006 IEEE Asian Solid-State Circuits Conference\",\"volume\":\"3 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 IEEE Asian Solid-State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASSCC.2006.357933\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE Asian Solid-State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASSCC.2006.357933","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 90nm 1-4.25-Gb/s Multi Data Rate Receiver for High Speed Serial Links
This paper describes the design of a receiver that supports the operation from 1 to 4.25-Gb/s, enabling a single macro to satisfy different protocols. The receiver performs equalization to compensate for interconnect ISI, achieves 10 mV sensitivity at 4.25-Gb/s by using offset corrected amplification, and performs clock-data-recovery with a digital algorithm that controls a recovered clock out of a phase interpolator. The receiver has been validated in 90 nm CMOS with 45 mW at 1.1 V supply voltage and demonstrated to achieve link over 30-meter AGW24 cable at 3.125 Gb/s with BER<10-5.
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