厚氧化物IO/ESD晶体管40nm晶圆制程漏损优化

2017 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia) Pub Date : 2017-10-01 DOI:10.1109/ICCE-ASIA.2017.8309321

Chinmayee Panigrahi, Mansi Rastogi, Kiran Gopal

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引用次数: 1

摘要

研究了40nm晶圆代工工艺下的厚氧化物IO/ESD晶体管，以减少漏损，同时保持面积效率和性能。栅极诱发漏漏(GIDL)和源漏漏是主要的漏漏源。本文给出了适合于IO/ESD设计的最佳结构和尺寸。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Leakage optimization of thick oxide IO/ESD transistors in 40nm global foundry process

Thick Oxide IO/ESD transistor in 40nm Global Foundry process is studied for reducing leakage while being area efficient and maintaining performance. Gate induced drain leakage(GIDL) and source-drain leakage were found to be the major leakage contributors. Optimum architecture and sizing are found for IO/ESD design and presented in this paper.

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来源期刊

2017 IEEE International Conference on Consumer Electronics-Asia (ICCE-Asia)

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