Enhanching memory performance in silicon nitride-based charge trapping memory device with Al2O3 blocking oxide and TiO2 capping layers

In this paper, we propose a novel charge trapping memory (CTM) device structure consisting of Si/TiO2/Al2O3/Si3N4/SiO2/Si (STANOS), where Al2O3 as blocking oxide and TiO2 as capping layers have been employed. The SILVACO Technology Computer-Aided Design (TCAD) simulation software is used to model and study the performance of the proposed CTM device. A comparative investigation of the memory performances amid the conventional silicon-oxide-nitride-oxide-silicon (SONOS) and the proposed STANOS is provided. It is found that the STANOS structure with Al2O3 blocking oxide and TiO2 capping layers shows faster programming and erasing speeds than the conventional SONOS structure. Al2O3 having higher barrier height impacts on better blocking efficiency with enhancing programming speed and TiO2 capping layer with modest dielectric constant suppresses electron injection during erasing operation. In addition, blocking layer with capping minimizes the electron emission during charge retention. These results will be useful to develop low-cost and low power consumption nitride-based CTM devices with better programming and erasing speeds.