AQFPTX: Adiabatic Quantum-Flux-Parametron Timing eXtraction Tool

The IARPA SuperTools program calls upon the need to development an electronic design automation (EDA) environment for superconductor electronics capable of supporting both dc-biased and ac-biased superconductor logic families. The AQFP logic family is an ac-biased logic family that differs substantially from canonical SFQ logic in how circuits are synchronized. Thus, it is necessary to develop new timing extraction methodologies to characterize AQFP logic cells. To this end, we developed a new timing extraction tool called AQFPTX (Adiabatic Quantum-Flux-Parametron Timing eXtraction). The tool uses a standardized test harness to characterize cells. Characterization is performed by sweeping the clock skew amount using an analog simulation engine. The timing information is automatically extracted from the analog waveforms and tabulated in a standard delay format (SDF) file which can be used by the EDA environment to perform timing closure of VLSI AQFP circuits.