M. van Delden, G. Hasenaecker, N. Pohl, K. Aufinger, T. Musch
{"title":"用于宽带毫米波频率斜坡合成的80 GHz可编程分频器","authors":"M. van Delden, G. Hasenaecker, N. Pohl, K. Aufinger, T. Musch","doi":"10.1109/RFIT.2015.7377927","DOIUrl":null,"url":null,"abstract":"A programmable frequency divider operating at input frequencies from DC to 80 GHz for the use in fractional-N synthesizers is presented. The division factor can be set to all integer values between 12 and 259 and is applied by an 8 bit parallel interface for fast modulation. The remarkably high input frequency in combination with the programmability is achieved by a dual-modulus concept and differential emitter-coupled logic with a consequent merging of logic gates into flip-flops. Among this, a reset function has been implemented to synchronize multiple synthesizers. The frequency divider has been realized in a SiGe BiCMOS technology (fr/fmax=250/360 GHz). The divider works at a supply voltage of 3.3 V with a power consumption of less than 390 mW.","PeriodicalId":422369,"journal":{"name":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"An 80 GHz programmable frequency divider for wideband mm-Wave frequency ramp synthesis\",\"authors\":\"M. van Delden, G. Hasenaecker, N. Pohl, K. Aufinger, T. Musch\",\"doi\":\"10.1109/RFIT.2015.7377927\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A programmable frequency divider operating at input frequencies from DC to 80 GHz for the use in fractional-N synthesizers is presented. The division factor can be set to all integer values between 12 and 259 and is applied by an 8 bit parallel interface for fast modulation. The remarkably high input frequency in combination with the programmability is achieved by a dual-modulus concept and differential emitter-coupled logic with a consequent merging of logic gates into flip-flops. Among this, a reset function has been implemented to synchronize multiple synthesizers. The frequency divider has been realized in a SiGe BiCMOS technology (fr/fmax=250/360 GHz). The divider works at a supply voltage of 3.3 V with a power consumption of less than 390 mW.\",\"PeriodicalId\":422369,\"journal\":{\"name\":\"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIT.2015.7377927\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Symposium on Radio-Frequency Integration Technology (RFIT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIT.2015.7377927","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An 80 GHz programmable frequency divider for wideband mm-Wave frequency ramp synthesis
A programmable frequency divider operating at input frequencies from DC to 80 GHz for the use in fractional-N synthesizers is presented. The division factor can be set to all integer values between 12 and 259 and is applied by an 8 bit parallel interface for fast modulation. The remarkably high input frequency in combination with the programmability is achieved by a dual-modulus concept and differential emitter-coupled logic with a consequent merging of logic gates into flip-flops. Among this, a reset function has been implemented to synchronize multiple synthesizers. The frequency divider has been realized in a SiGe BiCMOS technology (fr/fmax=250/360 GHz). The divider works at a supply voltage of 3.3 V with a power consumption of less than 390 mW.