D. Burns, I. Deram, J. Mello, J. Morgan, I. Wan, F. Robb
{"title":"npt - igbt可制造性优化","authors":"D. Burns, I. Deram, J. Mello, J. Morgan, I. Wan, F. Robb","doi":"10.1109/ISPSD.1996.509509","DOIUrl":null,"url":null,"abstract":"High-voltage NPT-IGBTs (non-punchthrough IGBTs) offer reasonable on-state voltages, high short-circuit ruggedness, and minimal turn-off losses without lifetime killing. In addition, NPT-IGBTs have the potential to reduce fabrication costs as compared to conventional epitaxial IGBTs because they are fabricated on low cost bulk silicon substrates, while conventional IGBTs utilize thick, expensive epitaxial layers. The key to realizing this potential cost savings, however, is the development of a manufacturable thin-wafer back end process flow. This paper will discuss NPT-IGBT process optimization, aimed at increased manufacturability. Starting material specifications, backside process optimization, and thin-wafer manufacturability issues are addressed.","PeriodicalId":377997,"journal":{"name":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","volume":"279 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1996-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"15","resultStr":"{\"title\":\"NPT-IGBT-optimizing for manufacturability\",\"authors\":\"D. Burns, I. Deram, J. Mello, J. Morgan, I. Wan, F. Robb\",\"doi\":\"10.1109/ISPSD.1996.509509\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"High-voltage NPT-IGBTs (non-punchthrough IGBTs) offer reasonable on-state voltages, high short-circuit ruggedness, and minimal turn-off losses without lifetime killing. In addition, NPT-IGBTs have the potential to reduce fabrication costs as compared to conventional epitaxial IGBTs because they are fabricated on low cost bulk silicon substrates, while conventional IGBTs utilize thick, expensive epitaxial layers. The key to realizing this potential cost savings, however, is the development of a manufacturable thin-wafer back end process flow. This paper will discuss NPT-IGBT process optimization, aimed at increased manufacturability. Starting material specifications, backside process optimization, and thin-wafer manufacturability issues are addressed.\",\"PeriodicalId\":377997,\"journal\":{\"name\":\"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings\",\"volume\":\"279 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1996-05-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"15\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.1996.509509\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"8th International Symposium on Power Semiconductor Devices and ICs. ISPSD '96. Proceedings","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.1996.509509","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
High-voltage NPT-IGBTs (non-punchthrough IGBTs) offer reasonable on-state voltages, high short-circuit ruggedness, and minimal turn-off losses without lifetime killing. In addition, NPT-IGBTs have the potential to reduce fabrication costs as compared to conventional epitaxial IGBTs because they are fabricated on low cost bulk silicon substrates, while conventional IGBTs utilize thick, expensive epitaxial layers. The key to realizing this potential cost savings, however, is the development of a manufacturable thin-wafer back end process flow. This paper will discuss NPT-IGBT process optimization, aimed at increased manufacturability. Starting material specifications, backside process optimization, and thin-wafer manufacturability issues are addressed.