高性能注入锁定分频器,采用0.18µm CMOS工艺,50 GHz LC交叉耦合振荡器

Sehyuk Ann, Jusang Park, Junho Yu, Namsoo Kim
{"title":"高性能注入锁定分频器,采用0.18µm CMOS工艺,50 GHz LC交叉耦合振荡器","authors":"Sehyuk Ann, Jusang Park, Junho Yu, Namsoo Kim","doi":"10.1109/SAPIW.2015.7237383","DOIUrl":null,"url":null,"abstract":"In this paper, a high performance frequency divider is introduced in an integrated CMOS phase-locked loop (PLL). An injection-locked frequency divider (ILFD) is designed with a current-mode logic (CML) frequency divider to obtain the broad-band and high frequency operation. LC cross-coupled oscillator operates at 50 GHz and ILFD is supposed to provide the operation of divide-by-2 (/2). ILFD has a similar structure with the oscillator to adjust the frequency alignment between the oscillator and ILFD. As the 2nd-stage divider, CML frequency divider is applied with an inductive peaking structure. The proposed frequency divider is applied in the conventional PLL which is integrated with 0.18 μm CMOS process. Simulation test shows that the /2 ILFD and /128 CML frequency divider is operated at the input frequency of 50 GHz with the power consumption of 30 mW.","PeriodicalId":231437,"journal":{"name":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","volume":"141 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"High performance injection-locked frequency divider with 50 GHz LC cross-coupled oscillator in 0.18 µm CMOS process\",\"authors\":\"Sehyuk Ann, Jusang Park, Junho Yu, Namsoo Kim\",\"doi\":\"10.1109/SAPIW.2015.7237383\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a high performance frequency divider is introduced in an integrated CMOS phase-locked loop (PLL). An injection-locked frequency divider (ILFD) is designed with a current-mode logic (CML) frequency divider to obtain the broad-band and high frequency operation. LC cross-coupled oscillator operates at 50 GHz and ILFD is supposed to provide the operation of divide-by-2 (/2). ILFD has a similar structure with the oscillator to adjust the frequency alignment between the oscillator and ILFD. As the 2nd-stage divider, CML frequency divider is applied with an inductive peaking structure. The proposed frequency divider is applied in the conventional PLL which is integrated with 0.18 μm CMOS process. Simulation test shows that the /2 ILFD and /128 CML frequency divider is operated at the input frequency of 50 GHz with the power consumption of 30 mW.\",\"PeriodicalId\":231437,\"journal\":{\"name\":\"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)\",\"volume\":\"141 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-05-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SAPIW.2015.7237383\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE 19th Workshop on Signal and Power Integrity (SPI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SAPIW.2015.7237383","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3

摘要

本文在集成式CMOS锁相环(PLL)中引入了一种高性能分频器。设计了一种注入锁定分频器(ILFD),采用电流模逻辑分频器(CML)实现宽带高频工作。LC交叉耦合振荡器工作在50 GHz, ILFD应该提供除以2(/2)的操作。ILFD具有与振荡器类似的结构,用于调节振荡器与ILFD之间的频率对准。CML分频器作为二级分频器,采用感应调峰结构。该分频器应用于集成了0.18 μm CMOS工艺的传统锁相环中。仿真测试表明,/2 ILFD和/128 CML分频器工作在50 GHz的输入频率下,功耗为30 mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
High performance injection-locked frequency divider with 50 GHz LC cross-coupled oscillator in 0.18 µm CMOS process
In this paper, a high performance frequency divider is introduced in an integrated CMOS phase-locked loop (PLL). An injection-locked frequency divider (ILFD) is designed with a current-mode logic (CML) frequency divider to obtain the broad-band and high frequency operation. LC cross-coupled oscillator operates at 50 GHz and ILFD is supposed to provide the operation of divide-by-2 (/2). ILFD has a similar structure with the oscillator to adjust the frequency alignment between the oscillator and ILFD. As the 2nd-stage divider, CML frequency divider is applied with an inductive peaking structure. The proposed frequency divider is applied in the conventional PLL which is integrated with 0.18 μm CMOS process. Simulation test shows that the /2 ILFD and /128 CML frequency divider is operated at the input frequency of 50 GHz with the power consumption of 30 mW.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信