{"title":"fsm特征监控方案效率比较","authors":"R. Rochet, R. Leveugle, G. Saucier","doi":"10.1109/ASPDAC.1995.486391","DOIUrl":null,"url":null,"abstract":"This paper addresses the detection of permanent and transient faults in complex VLSI circuits, with a particular focus on faults leading to sequencing errors. Several Finite State Machine implementations using signature monitoring for control-flow checking are compared in terms of error detection latency, theoretical error coverage, experimental error coverage and area overheads. Advantages and drawbacks of each approach are presented.","PeriodicalId":119232,"journal":{"name":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","volume":"106 6 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-08-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Efficiency comparison of signature monitoring schemes for FSMs\",\"authors\":\"R. Rochet, R. Leveugle, G. Saucier\",\"doi\":\"10.1109/ASPDAC.1995.486391\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper addresses the detection of permanent and transient faults in complex VLSI circuits, with a particular focus on faults leading to sequencing errors. Several Finite State Machine implementations using signature monitoring for control-flow checking are compared in terms of error detection latency, theoretical error coverage, experimental error coverage and area overheads. Advantages and drawbacks of each approach are presented.\",\"PeriodicalId\":119232,\"journal\":{\"name\":\"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair\",\"volume\":\"106 6 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-08-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASPDAC.1995.486391\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of ASP-DAC'95/CHDL'95/VLSI'95 with EDA Technofair","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.1995.486391","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Efficiency comparison of signature monitoring schemes for FSMs
This paper addresses the detection of permanent and transient faults in complex VLSI circuits, with a particular focus on faults leading to sequencing errors. Several Finite State Machine implementations using signature monitoring for control-flow checking are compared in terms of error detection latency, theoretical error coverage, experimental error coverage and area overheads. Advantages and drawbacks of each approach are presented.