基于130nm SiGe BiCMOS技术的26.5- 40ghz堆叠功率放大器

Chi Zhang, Zhiqun Li, Guoxiao Cheng, Huan Wang, Zhennan Li
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引用次数: 1

摘要

设计了一种基于130 nm SiGe BiCMOS工艺的26.5-40 GHz宽带堆叠功率放大器(PA)。采用三层堆叠的hbt,提高了输出功率和最优负载阻抗,有利于宽带输出匹配。低损耗宽带双向威尔金森功率合成器用于片上功率分合。仿真结果表明,在26.5 ~ 40 GHz范围内,输出1dB压缩功率(PldB)和饱和输出功率(PSAT)分别大于20.1dBm和23.4dBm。40%分数带宽的增益大于15.9dB,峰值功率增加效率(PAE)大于19.2%。当电源电压为4.8 V时,静态电流为58 mA。芯片尺寸为1.3 mm × 1.25 mm,包括所有衬垫。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 26.5-40 GHz Stacked Power Amplifier in 130 nm SiGe BiCMOS Technology
A 26.5-40 GHz broadband stacked power amplifier (PA) is designed in 130 nm SiGe BiCMOS process. By using triple-stacked HBTs, both output power and optimal load impedance increase, which is beneficial for wideband output matching. A low loss wideband two-way Wilkinson power combiner is used for on-chip power dividing and combining. EM simulation results show that from 26.5 to 40 GHz, the output 1- dB compressed power (PldB) and saturated output power (PSAT) are greater than 20.1dBm and 23.4dBm, respectively. The 40% fractional bandwidth PA has a gain over 15.9dB and peak power added efficiency (PAE) is greater than 19.2%. Static current is 58 mA for a supply voltage of 4.8 V. The chip size is 1.3 mm × 1.25 mm including all pads.
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