Chi Zhang, Zhiqun Li, Guoxiao Cheng, Huan Wang, Zhennan Li
{"title":"基于130nm SiGe BiCMOS技术的26.5- 40ghz堆叠功率放大器","authors":"Chi Zhang, Zhiqun Li, Guoxiao Cheng, Huan Wang, Zhennan Li","doi":"10.1109/CICTA.2018.8706045","DOIUrl":null,"url":null,"abstract":"A 26.5-40 GHz broadband stacked power amplifier (PA) is designed in 130 nm SiGe BiCMOS process. By using triple-stacked HBTs, both output power and optimal load impedance increase, which is beneficial for wideband output matching. A low loss wideband two-way Wilkinson power combiner is used for on-chip power dividing and combining. EM simulation results show that from 26.5 to 40 GHz, the output 1- dB compressed power (PldB) and saturated output power (PSAT) are greater than 20.1dBm and 23.4dBm, respectively. The 40% fractional bandwidth PA has a gain over 15.9dB and peak power added efficiency (PAE) is greater than 19.2%. Static current is 58 mA for a supply voltage of 4.8 V. The chip size is 1.3 mm × 1.25 mm including all pads.","PeriodicalId":186840,"journal":{"name":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","volume":"162 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 26.5-40 GHz Stacked Power Amplifier in 130 nm SiGe BiCMOS Technology\",\"authors\":\"Chi Zhang, Zhiqun Li, Guoxiao Cheng, Huan Wang, Zhennan Li\",\"doi\":\"10.1109/CICTA.2018.8706045\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 26.5-40 GHz broadband stacked power amplifier (PA) is designed in 130 nm SiGe BiCMOS process. By using triple-stacked HBTs, both output power and optimal load impedance increase, which is beneficial for wideband output matching. A low loss wideband two-way Wilkinson power combiner is used for on-chip power dividing and combining. EM simulation results show that from 26.5 to 40 GHz, the output 1- dB compressed power (PldB) and saturated output power (PSAT) are greater than 20.1dBm and 23.4dBm, respectively. The 40% fractional bandwidth PA has a gain over 15.9dB and peak power added efficiency (PAE) is greater than 19.2%. Static current is 58 mA for a supply voltage of 4.8 V. The chip size is 1.3 mm × 1.25 mm including all pads.\",\"PeriodicalId\":186840,\"journal\":{\"name\":\"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)\",\"volume\":\"162 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICTA.2018.8706045\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Conference on Integrated Circuits, Technologies and Applications (ICTA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICTA.2018.8706045","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 26.5-40 GHz Stacked Power Amplifier in 130 nm SiGe BiCMOS Technology
A 26.5-40 GHz broadband stacked power amplifier (PA) is designed in 130 nm SiGe BiCMOS process. By using triple-stacked HBTs, both output power and optimal load impedance increase, which is beneficial for wideband output matching. A low loss wideband two-way Wilkinson power combiner is used for on-chip power dividing and combining. EM simulation results show that from 26.5 to 40 GHz, the output 1- dB compressed power (PldB) and saturated output power (PSAT) are greater than 20.1dBm and 23.4dBm, respectively. The 40% fractional bandwidth PA has a gain over 15.9dB and peak power added efficiency (PAE) is greater than 19.2%. Static current is 58 mA for a supply voltage of 4.8 V. The chip size is 1.3 mm × 1.25 mm including all pads.