Improvement of multi-digital multiplicating devices structures in different theoretical and numerical bases

The article proposes methods for improving the structures of multi-bit multipliers, which are characterized by increased speed, reduced structural complexity of the device and reduced structural complexity of inputs and outputs depending on the bit multipliers (512-2048 bits), respectively (1024- 4096) times, compared with known multipliers based on classic single-digit full adders. Optimization of structures of multi-bit multipliers is offered. Comparative estimates of structural, functional and relative functional and structural complexities of their circuit implementations are given. The use of optimized circuit solutions of multipliers allows to significantly improve the system characteristics of complex computing devices with a large number of such components in the crystals of microelectronic technologies.