DPA resistance analysis of the cryptographic S-box implementation in static CMOS and TDPL logic style

Cryptography is the art of realizing security by the strength of mathematics involved in the security algorithm, the security is compromised by the mathematics of cryptanalysis using the side channel attacks. Differential power analysis (DPA) is the most effective form of side channel power analysis, which analyses the power consumption of the cryptographic device statistically and reveals the secret information. This paper investigates the implementation of the S-BOX with the DPA resistant logical style, namely, the Three Phase Dual rail Pre-charge logic (TDPL) which makes the power consumption of the device insensitive to intermediate values. To make the power consumption constant an additional phase is added in addition to the pre-charge and evaluation phases of the three phase dual rail logic. In this paper, the implementation of the S-BOX is carried out in both the static CMOS logic and the TDPL logic to compare their DPA resistance. It is proved that the static CMOS logic is more vulnerable to power analysis than the considered three phase logic. The correlation analysis is performed to estimate the property of the DPA resistance of the S-box implementation.