{"title":"一种有效的签名加载机制,用于内存修复","authors":"V. Sargsyan","doi":"10.1109/EWDTS.2014.7027061","DOIUrl":null,"url":null,"abstract":"Built-in Self-Test (BIST) and Built-In Self-Repair (BISR) have been widely used for embedded memories test and repair purposes. One of the disadvantages of these circuits is the memory repair signature delivery process at what is typically known as hard repair flow. In this paper, a memory repair signature loading mechanism is introduced, which significantly reduces memory repair organization time.","PeriodicalId":272780,"journal":{"name":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","volume":"2018 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An efficient signature loading mechanism for memory repair\",\"authors\":\"V. Sargsyan\",\"doi\":\"10.1109/EWDTS.2014.7027061\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Built-in Self-Test (BIST) and Built-In Self-Repair (BISR) have been widely used for embedded memories test and repair purposes. One of the disadvantages of these circuits is the memory repair signature delivery process at what is typically known as hard repair flow. In this paper, a memory repair signature loading mechanism is introduced, which significantly reduces memory repair organization time.\",\"PeriodicalId\":272780,\"journal\":{\"name\":\"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)\",\"volume\":\"2018 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EWDTS.2014.7027061\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of IEEE East-West Design & Test Symposium (EWDTS 2014)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EWDTS.2014.7027061","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An efficient signature loading mechanism for memory repair
Built-in Self-Test (BIST) and Built-In Self-Repair (BISR) have been widely used for embedded memories test and repair purposes. One of the disadvantages of these circuits is the memory repair signature delivery process at what is typically known as hard repair flow. In this paper, a memory repair signature loading mechanism is introduced, which significantly reduces memory repair organization time.