Fast Modeling of the L2 Cache Reuse Distance Histograms from Software Traces

As the speed gap between the CPU and the main memory keeps increasing, multi-level caches are widely used in modern processors to improve the memory access latency. Therefore, modeling behaviors of the downstream caches becomes a critical part of the processor performance evaluation. In this paper, we propose a fast, yet accurate, L2 cache reuse distance histogram model without time-consuming full simulations, which can be utilized to evaluate the L2 cache miss rate with the Random and LRU replacement policies. The inputs of our model only need to be profiled once and can be reused for evaluations of different L2 cache configurations. To evaluate our model, we compare the output L2 RDH from our model and that of gem5 cycle-accurate simulations. When used to evaluate the L2 cache miss rates, the average absolute error is 3% for SPEC2006 benchmarks.