一种模糊逻辑推理处理器

Third International Conference on Industrial Fuzzy Control and Intelligent Systems Pub Date : 1900-01-01 DOI:10.1109/IFIS.1993.324186

J. Fattaruso, S. Mahant-Shetti, J. Brock Barton

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引用次数: 28

摘要

介绍了一种以0.8 /spl μ m CMOS工艺制作的模数混合模糊逻辑推理机芯片。与处理器的接口类似于静态RAM，模糊逻辑推理的计算由一组模拟电荷域电路在存储器位置之间并行执行。提供8个输入和4个输出，最多可将32条规则编程到芯片中。包括质心去模糊化在内的所有规则的推理结果，可以用2 /spl mu/sec.>来计算

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A fuzzy logic inference processor

A mixed analog-digital fuzzy logic inference engine chip fabricated in an O.8 /spl mu/m CMOS process is described. The interface to the processor behaves like a static RAM, and computation of the fuzzy logic inference is performed between memory locations in parallel by an array of analog charge-domain circuits. Eight inputs and four outputs are provided, and up to 32 rules may be programmed into the chip. The results of the inference over all rules including a center-of-mass defuzzification, may be computed in 2 /spl mu/sec.<>

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Third International Conference on Industrial Fuzzy Control and Intelligent Systems

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