Jitters through dual clocks: An effective Entropy Source for True Random Number Generation

True random number generators (TRNG) have an appreciable demand in key generation of crypto processors. FPGA based TRNGs offer various advantages for generation, packing and storage. Metastability, jitter, race around and memory collision are some of the entropy sources for extraction of true randomness. In this work, jitter extraction is the prime focus for randomness harvesting. Two different frequencies have been generated by Onchip PLL of FPGA which were used in an asynchronous manner for random bit generation. Two Flip-flops have been used in this design after which post processing unit enhances the randomness. Both Von - Neumann Corrector as well as 1D logistic map have been experimented as post processing functions. Randomness of the numbers was tested and ensured by performing entropy analysis as well as NIST tests. This proposed TRNG has been designed using VHDL and implemented on Altera Cyclone II EP2C35F672C6N FPGA consuming 1298 logic elements with a throughput of 26.84 Mbps.