{"title":"具有重要的微电子系统设计经验,适合CS, CE和EE学生","authors":"C. Purdy","doi":"10.1109/MSE.1997.612586","DOIUrl":null,"url":null,"abstract":"Using structured design techniques borrowed from software programming, beginning circuit designers at the University of Cincinnati consistently create correct, working chips containing several thousand gates. Careful choice of topics and easy-to-use tools allow consideration of physical behaviour and optimization techniques and also prepare students for more advanced study of circuit design. Chip testing is accomplished with user-friendly software and hardware created locally by a group of M.S. Students. Initially targeting CMOS tiny chip designs, course materials have recently been modified for programmable logic devices (PLDs). Immediate testability of PLDs provides better feedback, and the associated design tools support high-level hardware description languages (HDLs). This also makes multi-chip student projects feasible.","PeriodicalId":120048,"journal":{"name":"Proceedings of International Conference on Microelectronic Systems Education","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1997-07-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Significant microelectronics systems design experience for a heterogeneous class of CS, CE, and EE students\",\"authors\":\"C. Purdy\",\"doi\":\"10.1109/MSE.1997.612586\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Using structured design techniques borrowed from software programming, beginning circuit designers at the University of Cincinnati consistently create correct, working chips containing several thousand gates. Careful choice of topics and easy-to-use tools allow consideration of physical behaviour and optimization techniques and also prepare students for more advanced study of circuit design. Chip testing is accomplished with user-friendly software and hardware created locally by a group of M.S. Students. Initially targeting CMOS tiny chip designs, course materials have recently been modified for programmable logic devices (PLDs). Immediate testability of PLDs provides better feedback, and the associated design tools support high-level hardware description languages (HDLs). This also makes multi-chip student projects feasible.\",\"PeriodicalId\":120048,\"journal\":{\"name\":\"Proceedings of International Conference on Microelectronic Systems Education\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-07-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of International Conference on Microelectronic Systems Education\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MSE.1997.612586\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of International Conference on Microelectronic Systems Education","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MSE.1997.612586","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
摘要
辛辛那提大学(University of Cincinnati)的初级电路设计师利用借鉴于软件编程的结构化设计技术,不断地创造出包含数千个门的正确的工作芯片。精心选择的主题和易于使用的工具允许考虑物理行为和优化技术,也为学生准备更高级的电路设计研究。芯片测试是由一群M.S.学生在本地创建的用户友好的软件和硬件完成的。最初的目标是CMOS微型芯片设计,课程材料最近已修改为可编程逻辑器件(pld)。pld的即时可测试性提供了更好的反馈,相关的设计工具支持高级硬件描述语言(hdl)。这也使得多芯片学生项目变得可行。
Significant microelectronics systems design experience for a heterogeneous class of CS, CE, and EE students
Using structured design techniques borrowed from software programming, beginning circuit designers at the University of Cincinnati consistently create correct, working chips containing several thousand gates. Careful choice of topics and easy-to-use tools allow consideration of physical behaviour and optimization techniques and also prepare students for more advanced study of circuit design. Chip testing is accomplished with user-friendly software and hardware created locally by a group of M.S. Students. Initially targeting CMOS tiny chip designs, course materials have recently been modified for programmable logic devices (PLDs). Immediate testability of PLDs provides better feedback, and the associated design tools support high-level hardware description languages (HDLs). This also makes multi-chip student projects feasible.