Modeling and co-simulation of I/O interconnects for on-chip and off-chip EMI prediction

In this paper, modeling and co-simulation methodology is proposed to predict EMI noise from the switching activity of on-chip interconnects. The proposed model includes the model for I/O driver and the on-chip interconnect load, the PKG and the test PCB, and the conducted and radiated EMI simulation. Using the simulation results of the proposed model, the I/O driver and the interconnect design can be optimized for minimum chip level EMI noise.