Design of 2.5Gb/s non-PLL-type all-digital clock recovery circuit

This paper describes the architecture and design of 2.5Gb/s non-PLL-type all-digital clock recovery circuit. The proposed circuit is non-PLL-type and designed in fully digital style to provide faster acquisition time and better scalability and portability. Output jitter would not be accumulated since the proposed circuit recovers output clock for every transition of input data. Furthermore, it can recover the final output clock from potential candidate clock signals without any special elaborated techniques and the acquisition time is fast enough. The proposed circuit is designed using 130nm, 1.2V CMOS technology and simulated for 27 −1 pseudo random bit sequence data at 2.5Gb/s with HSpice circuit simulator. The phase shifts in recovered clock for input data skew is within ±40ps, and peak-to-peak jitter and RMS jitter are 49ps and 4.5ps, respectively.