生成VHDL模型的高级测试台

Proceedings ECBS'99. IEEE Conference and Workshop on Engineering of Computer-Based Systems Pub Date : 1999-03-07 DOI:10.1109/ECBS.1999.755873

S. Deniziak, K. Sapiecha

{"title":"生成VHDL模型的高级测试台","authors":"S. Deniziak, K. Sapiecha","doi":"10.1109/ECBS.1999.755873","DOIUrl":null,"url":null,"abstract":"A new technique for automatic generation of VHDL testbenches is presented. Testbenches are generated using stimuli description in the WEGA language (K. Sapiecha and S. Deniziak, 1996) and VHDL entity declaration of the model under test. This technique makes it possible to reduce the length and complexity of testbenches by the factor of 10, on average. Moreover, describing testbenches in WEGA is much easier and flexible than describing them directly in VHDL. The source WEGA code is also more readable.","PeriodicalId":229109,"journal":{"name":"Proceedings ECBS'99. IEEE Conference and Workshop on Engineering of Computer-Based Systems","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"High level testbench generation for VHDL models\",\"authors\":\"S. Deniziak, K. Sapiecha\",\"doi\":\"10.1109/ECBS.1999.755873\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new technique for automatic generation of VHDL testbenches is presented. Testbenches are generated using stimuli description in the WEGA language (K. Sapiecha and S. Deniziak, 1996) and VHDL entity declaration of the model under test. This technique makes it possible to reduce the length and complexity of testbenches by the factor of 10, on average. Moreover, describing testbenches in WEGA is much easier and flexible than describing them directly in VHDL. The source WEGA code is also more readable.\",\"PeriodicalId\":229109,\"journal\":{\"name\":\"Proceedings ECBS'99. IEEE Conference and Workshop on Engineering of Computer-Based Systems\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-03-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings ECBS'99. IEEE Conference and Workshop on Engineering of Computer-Based Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECBS.1999.755873\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings ECBS'99. IEEE Conference and Workshop on Engineering of Computer-Based Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECBS.1999.755873","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

提出了一种自动生成VHDL测试台架的新技术。测试平台是使用WEGA语言(K. Sapiecha和S. Deniziak, 1996)中的刺激描述和被测模型的VHDL实体声明生成的。这种技术使得平均将测试台的长度和复杂性减少10倍成为可能。此外，在WEGA中描述测试平台比直接在VHDL中描述更容易和灵活。源WEGA代码也更可读。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

High level testbench generation for VHDL models

A new technique for automatic generation of VHDL testbenches is presented. Testbenches are generated using stimuli description in the WEGA language (K. Sapiecha and S. Deniziak, 1996) and VHDL entity declaration of the model under test. This technique makes it possible to reduce the length and complexity of testbenches by the factor of 10, on average. Moreover, describing testbenches in WEGA is much easier and flexible than describing them directly in VHDL. The source WEGA code is also more readable.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings ECBS'99. IEEE Conference and Workshop on Engineering of Computer-Based Systems

自引率

0.00%

发文量