Comparison of existing & proposed SOI MOSFET device structures for minimizing total dose radiation damage

This paper compares various SOI MOSFET device structures with regard to their ability to mitigate total ionizing dose (TID) radiation effects. Three-dimensional rad-hardening of the dielectrics surrounding the channel and/or direct control of the channel surfaces is required, in order to reduce source-to-drain leakage caused by radiation-induced charges which accumulate at the dielectric interfaces surrounding the device. In addition, it is highly desirable to provide dynamic adjustment of the device's electrical characteristics in order to compensate for these TID effects as well as other wearout effects. A new, ultra-low-power SOI RF-CMOS technology from American Semiconductor that is able to operate reliably in high radiation environments is also be described. This double-gated 0.18 /spl mu/m technology permits dynamically "self-repairing" circuits, which are tolerant of large lifetime total doses of radiation. This technology also features MOSFETs and lateral BJT's with undoped channel/base regions that are appropriate for cryogenic operation.