SI-PI cosimulation analysis of dual referencing and VSS-Referencing memory bus

Assessing the I/O performance delta between dual-referencing and ground-referencing schemes is needed to enable a lower layer count on either board or package, thereby reducing the overall platform cost. Existing methodologies attempted in quantifying impact simultaneously on both PI (Power Integrity) and SI (Signal Integrity) [1], [2] although the work is usually focused on I/O power delivery impact and rarely on actually quantifying impact of different referencing schemes [1]. An initial comparison between different referencing schemes on PKG (package) and BRD (board) has been performed. Then a further analysis has been performed to characterize a PKG with Dual referencing and VSS-Referencing.