AT&T DSP3并行信号处理器的应用与封装

[1992] Proceedings of the International Conference on Application Specific Array Processors Pub Date : 1992-08-04 DOI:10.1109/ASAP.1992.218562

R. Shively, L. J. Wu

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引用次数: 4

摘要

实现高度并行MIMD处理器架构的潜在性能主要取决于网络结构的速度和路由能力。描述了AT&T DSP3处理器的路由网络，并说明了如何配置40兆字节/秒的链路以满足各种应用需求。紧凑的封装有助于扩展到非常大的配置。硅对硅多芯片模块和一种新颖的三维垂直互连技术被用于将DSP3重新封装到超密集处理器中。

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Application and packaging of the AT&T DSP3 parallel signal processor

Achieving the potential performance of highly parallel MIMD processor architectures is critically dependent on both the speed and routing capabilities of the network fabric. The routing network of the AT&T DSP3 processor is described together with an indication of how the 40 megabyte/s links can be configured to meet diverse application requirements. Scaling to very large configurations is aided by compact packaging. Silicon-on-silicon multi-chip modules together with a novel three-dimensional vertical interconnection technology are being used to repackage the DSP3 into the ultra-dense processor.<>

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[1992] Proceedings of the International Conference on Application Specific Array Processors

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