具有节能通管逻辑(EEPL)的低功耗7位串行计数器设计

Proceedings of Third International Conference on Electronics, Circuits, and Systems Pub Date : 1996-10-13 DOI:10.1109/ICECS.1996.584563

Minyoung Song, Geun-Soon Kang, Seongwon Kim, Euro Joe, Bong-Soon Kang

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引用次数: 1

摘要

提出了一种节能通管逻辑(EEPL)。采用pMOS开关的再生正反馈原理，与CPL和SRPL相比，我们降低了功率。为了验证EEPL的性能，设计了一个低功耗的7位串行计数器。工作速度约为250 MHz，采用0.6 /spl mu/m 3.3 V CMOS工艺。

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Design of a low power 7-bit serial counter with energy economized pass-transistor logic (EEPL)

Energy Economized Pass-transistor Logic (EEPL) is proposed. Adopting the principle of regenerative positive feedback with pMOS switches, we reduce the power in comparison with CPL and SRPL. To demonstrate the performance of EEPL, a low power 7-bit serial counter is designed. The operating speed is about 250 MHz with 0.6 /spl mu/m 3.3 V CMOS process.

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Proceedings of Third International Conference on Electronics, Circuits, and Systems

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