{"title":"先进信息技术中微电子系统复杂布局对象的几何模型","authors":"S. Mironov, A. O. Monko","doi":"10.1109/SCM.2017.7970518","DOIUrl":null,"url":null,"abstract":"The work is devoted to the improvement of methods for designing the LSI layout in conditions of design rules uncertainty using layout compaction algorithms based on the virtual coordinate grid. The result is a layout model of the transistor and its geometric description that reduces the complexity of layout compaction algorithms based on a virtual coordinate grid.","PeriodicalId":315574,"journal":{"name":"2017 XX IEEE International Conference on Soft Computing and Measurements (SCM)","volume":"126 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Geometric models of complex layout objects of microelectronic systems in advanced information technologies\",\"authors\":\"S. Mironov, A. O. Monko\",\"doi\":\"10.1109/SCM.2017.7970518\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The work is devoted to the improvement of methods for designing the LSI layout in conditions of design rules uncertainty using layout compaction algorithms based on the virtual coordinate grid. The result is a layout model of the transistor and its geometric description that reduces the complexity of layout compaction algorithms based on a virtual coordinate grid.\",\"PeriodicalId\":315574,\"journal\":{\"name\":\"2017 XX IEEE International Conference on Soft Computing and Measurements (SCM)\",\"volume\":\"126 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 XX IEEE International Conference on Soft Computing and Measurements (SCM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SCM.2017.7970518\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 XX IEEE International Conference on Soft Computing and Measurements (SCM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SCM.2017.7970518","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Geometric models of complex layout objects of microelectronic systems in advanced information technologies
The work is devoted to the improvement of methods for designing the LSI layout in conditions of design rules uncertainty using layout compaction algorithms based on the virtual coordinate grid. The result is a layout model of the transistor and its geometric description that reduces the complexity of layout compaction algorithms based on a virtual coordinate grid.