高效并行有限场模乘法器

3rd International Symposium on Image and Signal Processing and Analysis, 2003. ISPA 2003. Proceedings of the Pub Date : 2003-09-18 DOI:10.1109/ISPA.2003.1296936

Hua Li

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引用次数: 0

摘要

本文定义了一种具有不可约全一多项式(AOP)的冗余正则基表示。基于所提出的冗余表示，可以简化乘法运算。提出了一种快速位并行乘法器，该乘法器需要(m + 1)/sup 2/ 2输入与门和m(m + 1) 2输入异或门。延时为T/下标AND/ + [log/下标2/(m + 1)]T/下标XOR/。所提出的架构是高度模块化的，非常适合高速VLSI的实现。

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Efficient parallel finite field modular multiplier

In tins paper, a redundant canonical basis representation with the irreducible all one polynomial (AOP) is defined. Based on the proposed redundant representation, the multiplication operation can be simplified. A fast bit-parallel multipliers is proposed that require (m + 1)/sup 2/ 2-input AND gates and m(m + 1) 2-input XOR gates. The time delay is T/sub AND/ + [log/sub 2/(m + 1)]T/sub XOR/. The proposed architectures are highly modular and well suited for high speed VLSI implementations.

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3rd International Symposium on Image and Signal Processing and Analysis, 2003. ISPA 2003. Proceedings of the

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