{"title":"基于SOI CMOS技术的折叠开关混频器","authors":"Ayobami B. Iji, Xi Zhu, M. Heimlich","doi":"10.1109/MWSCAS.2012.6292056","DOIUrl":null,"url":null,"abstract":"A wideband 3.5 to 5.5GHz low voltage folded-switching mixer is implemented in 0.25um SOI CMOS technology. The post-layout simulation of the designed mixer at 4.5GHz has noise figure (NF) of 9.6dB, input IP3 of -9dBm, conversion gain (CG) of 10.9dB and total current consumption including bias is 4.5mA under 1.5V supply voltage. The designed mixer can also operate under 1V supply voltage with relatively small linear performances degradation. The chip area is 0.55×0.5mm2. Due to high-resistivity silicon substrate, buried oxide isolation and low threshold voltage, SOI CMOS technology offers significant performance improvements for mixers, which makes the designed mixer well suitable for low voltage and low power applications.","PeriodicalId":324891,"journal":{"name":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-09-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A folded-switching mixer in SOI CMOS technology\",\"authors\":\"Ayobami B. Iji, Xi Zhu, M. Heimlich\",\"doi\":\"10.1109/MWSCAS.2012.6292056\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A wideband 3.5 to 5.5GHz low voltage folded-switching mixer is implemented in 0.25um SOI CMOS technology. The post-layout simulation of the designed mixer at 4.5GHz has noise figure (NF) of 9.6dB, input IP3 of -9dBm, conversion gain (CG) of 10.9dB and total current consumption including bias is 4.5mA under 1.5V supply voltage. The designed mixer can also operate under 1V supply voltage with relatively small linear performances degradation. The chip area is 0.55×0.5mm2. Due to high-resistivity silicon substrate, buried oxide isolation and low threshold voltage, SOI CMOS technology offers significant performance improvements for mixers, which makes the designed mixer well suitable for low voltage and low power applications.\",\"PeriodicalId\":324891,\"journal\":{\"name\":\"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)\",\"volume\":\"32 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-09-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2012.6292056\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2012.6292056","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 5
摘要
采用0.25um SOI CMOS技术实现了宽带3.5 ~ 5.5GHz低压折叠开关混频器。设计的混频器在4.5GHz下的布局后仿真,噪声系数(NF)为9.6dB,输入IP3为-9dBm,转换增益(CG)为10.9dB,在1.5V电源电压下,包括偏置在内的总电流消耗为4.5mA。所设计的混频器也可以在1V电源电压下工作,线性性能下降较小。芯片面积为0.55×0.5mm2。由于高电阻率硅衬底、埋地氧化物隔离和低阈值电压,SOI CMOS技术为混频器提供了显着的性能改进,使设计的混频器非常适合低电压和低功耗应用。
A wideband 3.5 to 5.5GHz low voltage folded-switching mixer is implemented in 0.25um SOI CMOS technology. The post-layout simulation of the designed mixer at 4.5GHz has noise figure (NF) of 9.6dB, input IP3 of -9dBm, conversion gain (CG) of 10.9dB and total current consumption including bias is 4.5mA under 1.5V supply voltage. The designed mixer can also operate under 1V supply voltage with relatively small linear performances degradation. The chip area is 0.55×0.5mm2. Due to high-resistivity silicon substrate, buried oxide isolation and low threshold voltage, SOI CMOS technology offers significant performance improvements for mixers, which makes the designed mixer well suitable for low voltage and low power applications.