Approach to the numerical solution of Lorenz system on SoC FPGA

In this paper is presented the implementation of a FPGA based heterogeneous system for the approach to the numerical solution of the Lorenz system by Euler's method. Unlike similar works, high level design tools as System Generator or DSP Builder are not used. The system is implemented on a ZedBoard Zynq Evaluation and Development Kit over Vivado Design Suite. It takes advantage of the SoC FPGA architecture, where a custom IP described in VHDL for the programmable logic section interacts with the ZYNQ-7processing system through AXI4-Lite interface. Operations are performed using a 32-bit floating-point format with rounding to the nearest value. Performance and numerical results analysis for the sequential algorithm execution over the Zynq-7000 ARM Cortex A9 core and the concurrent execution using the heterogeneous system are presented and compared. The validation of the developed system is made through the comparison between the approach to the numerical solution obtained with the SoC FPGA and MAT-LAB simulation is performed for different initial conditions and system parameters.