ESD reliability improvement by the source-discrete placement in a 45-V pLDMOS-SCR (npn-type)

In this paper, Electrostatic-Discharge (ESD) reliability study of 45-V HV pLDMOS devices with the source-side discrete islands is investigated. A pure pLDMOS transistor is always frail in ESD harms (It2= 0.107-A). However, if a pLDMOS device with two embedded SCRs (drain side npn-arranged); the corresponding It2 current can be upgraded to 0.644-A. Furthermore, as a pLDMOS-SCR (npn-arranged stripe type) extra with the source discrete technique, the trigger voltage (Vt1) values of these pLDMOS-SCR devices have slowly increased with the OD-rows number decreased. And, a highest Vt1 value on DIS-3 of 48.49-V can be obtained. Meanwhile, the best secondary breakdown current (It2) value is 4.032-A. Then, a source discrete technique is good for ESD robustness in these pLDMOS-SCR compound devices.