一种用于具有逻辑lsi的合并存储器的存储器访问系统

AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) Pub Date : 1900-01-01 DOI:10.1109/APASIC.1999.824114

Young-Sik Kim, T. Han, Shin-Dug Kim

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引用次数: 2

摘要

本文提出了一种新的内存访问控制方案——延迟预充方案，通过提高片上DRAM的多块访问页面命中率来提高片上DRAM的性能。通过执行驱动仿真，该体系结构比分层多银行体系结构和传统银行体系结构表现出更高的性能。在典型应用中，该方案可将传统DRAM的缓存填充时间和CPI分别降低26.9%和6.2%。

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A memory access system for merged memory with logic LSIs

This paper proposes a new memory access control scheme called delayed precharge scheme, to improve the performance of on-chip DRAM's by increasing the DRAM page hit ratio for multiple block accesses. This architecture shows higher performance than the hierarchical multi-bank architecture as well as the conventional bank architecture by execution-driven simulation. The proposed scheme could reduce the cache refill time and CPI obtained by the conventional DRAM by 26.9% and 6.2% respectively in typical applications.

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AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360)

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