用于DS-CDMA超宽带收发器的6位5.4 gsamples /s CMOS D/ a转换器设计

Shen Wang, D. Ha, S. S. Choi
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引用次数: 12

摘要

本文提出了一种基于IBM 0.13 /spl mu/m CMOS技术的用于DS-CDMA超宽带收发器的6位5.4 gsamples /s D/ a转换器的设计。高转换率和1.5 V的低电源电压使设计成为一个挑战。为了减少电路的时间常数,我们提出了一种两级电流转向拓扑,其中电阻性和容性负载的分布在两级上是平衡的。我们还提出了一种折叠级联码电流源单元,它消除了控制开关信号交叉点的需要,并最大限度地减少了数字馈通。电流源电池在不牺牲净空的情况下做到这一点,因此该电路适用于低电源电压。进行了布局后仿真来估计性能。在5.4 Gsamples/s的转换速率下,三种不同信号频率下的无杂散动态范围(SFDR)均大于38 dB。积分非线性(INL)和微分非线性(DNL)均保持在0.3 LSB以内。该布局占用的有效面积很小,仅为110 /spl亩/米/次/ 90 /spl亩/米,D/ a转换器功耗仅为20兆瓦。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design of a 6-bit 5.4-Gsamples/s CMOS D/A converter for DS-CDMA UWB transceivers
This paper presents a design of a 6-bit 5.4-Gsamples/s D/A converter in IBM 0.13 /spl mu/m CMOS technology for DS-CDMA UWB transceivers. The high conversion rate and low supply voltage of 1.5 V make the design a challenge. To reduce the time constant of the circuit, we propose a two-stage current-steering topology, in which the distribution of the resistive and capacitive loads is balanced at the two stages. We also propose a folded-cascode current source cell that eliminates the need to control the crossing-points of the switch signals and minimizes the digital feedthrough. The current source cell does this without sacrificing headroom, so the circuit is suitable for a low supply voltage. Post-layout simulation has been performed to estimate performance. At the conversion rate of 5.4 Gsamples/s, the spurious free dynamic range (SFDR) is greater than 38 dB for three different signal frequencies. Both the integral nonlinearity (INL) and differential nonlinearity (DNL) stay within 0.3 LSB. The layout occupies a small active area of 110 /spl mu/m /spl times/ 90 /spl mu/m, and the D/A converter consumes only 20 mW of power.
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