Architecture of the multi-tap-delay-line time-interval measurement module implemented in FPGA device

This paper describes the architecture of a Multi‐Tap‐Delay‐Line (MTDL) time‐interval measurement module of high resolution implemented in a single FPGA device. The new architecture of the measurement module enables to collect sixteen time‐stamps during a single measuring cycle. It means that the measured time‐interval can be precisely interpolated from the collection of the sixteen time‐stamps after each measuring cycle. Such architecture of the measurement module leads directly to an increased resolution, to a limited total measurement time and a decreased duty cycle of the measurement instrument.