一个10-b, 300 ms /s功率DAC, 6-Vpp差分摆幅

2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2013-06-02 DOI:10.1109/RFIC.2013.6569550

M. Mehrjoo, J. Buckwalter

{"title":"一个10-b, 300 ms /s功率DAC, 6-Vpp差分摆幅","authors":"M. Mehrjoo, J. Buckwalter","doi":"10.1109/RFIC.2013.6569550","DOIUrl":null,"url":null,"abstract":"A 10-bit digital-to-analog converter (DAC) is presented that delivers 6-Vpp into a 100-Ω differential load. The circuit is implemented in 45-nm CMOS SOI, which provides benefits for using a FET-stack current buffer. The measured DNL is better than 0.44 LSB. The DAC consumes 476 mW and achieves a peak SFDR of 54.4 dB and a minimum IM3 of -55.6 dBc. This DAC demonstrates the largest output swing and highest power efficiency for a highresolution (>8b), high-speed (>100MS/s) DAC.","PeriodicalId":203521,"journal":{"name":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"A 10-b, 300-MS/s power DAC with 6-Vpp differential swing\",\"authors\":\"M. Mehrjoo, J. Buckwalter\",\"doi\":\"10.1109/RFIC.2013.6569550\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 10-bit digital-to-analog converter (DAC) is presented that delivers 6-Vpp into a 100-Ω differential load. The circuit is implemented in 45-nm CMOS SOI, which provides benefits for using a FET-stack current buffer. The measured DNL is better than 0.44 LSB. The DAC consumes 476 mW and achieves a peak SFDR of 54.4 dB and a minimum IM3 of -55.6 dBc. This DAC demonstrates the largest output swing and highest power efficiency for a highresolution (>8b), high-speed (>100MS/s) DAC.\",\"PeriodicalId\":203521,\"journal\":{\"name\":\"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"volume\":\"10 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-06-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC.2013.6569550\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2013.6569550","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 9

摘要

提出了一种10位数模转换器(DAC)，可将6-Vpp传输到100-Ω差分负载。该电路在45纳米CMOS SOI中实现，这为使用场效应晶体管堆栈电流缓冲器提供了好处。实测DNL优于0.44 LSB。该DAC功耗为476 mW，峰值SFDR为54.4 dB，最小IM3为-55.6 dBc。该DAC具有高分辨率(>8b)、高速(>100MS/s) DAC的最大输出摆幅和最高功率效率。

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A 10-b, 300-MS/s power DAC with 6-Vpp differential swing

A 10-bit digital-to-analog converter (DAC) is presented that delivers 6-Vpp into a 100-Ω differential load. The circuit is implemented in 45-nm CMOS SOI, which provides benefits for using a FET-stack current buffer. The measured DNL is better than 0.44 LSB. The DAC consumes 476 mW and achieves a peak SFDR of 54.4 dB and a minimum IM3 of -55.6 dBc. This DAC demonstrates the largest output swing and highest power efficiency for a highresolution (>8b), high-speed (>100MS/s) DAC.

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2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

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