超窄硅纳米线栅极全能CMOS器件:直径、通道取向和低温对器件性能的影响

2006 International Electron Devices Meeting Pub Date : 2006-12-01 DOI:10.1109/IEDM.2006.346840

N. Singh, F. Y. Lim, W. Fang, S. Rustagi, L. Bera, A. Agarwal, C. Tung, K. Hoe, S. R. Omampuliyur, D. Tripathi, A. Adeyeye, G. Lo, N. Balasubramanian, D. Kwong

{"title":"超窄硅纳米线栅极全能CMOS器件:直径、通道取向和低温对器件性能的影响","authors":"N. Singh, F. Y. Lim, W. Fang, S. Rustagi, L. Bera, A. Agarwal, C. Tung, K. Hoe, S. R. Omampuliyur, D. Tripathi, A. Adeyeye, G. Lo, N. Balasubramanian, D. Kwong","doi":"10.1109/IEDM.2006.346840","DOIUrl":null,"url":null,"abstract":"Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well","PeriodicalId":366359,"journal":{"name":"2006 International Electron Devices Meeting","volume":"105 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"156","resultStr":"{\"title\":\"Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance\",\"authors\":\"N. Singh, F. Y. Lim, W. Fang, S. Rustagi, L. Bera, A. Agarwal, C. Tung, K. Hoe, S. R. Omampuliyur, D. Tripathi, A. Adeyeye, G. Lo, N. Balasubramanian, D. Kwong\",\"doi\":\"10.1109/IEDM.2006.346840\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well\",\"PeriodicalId\":366359,\"journal\":{\"name\":\"2006 International Electron Devices Meeting\",\"volume\":\"105 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"156\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2006 International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2006.346840\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2006.346840","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 156

摘要

采用不同晶向的纳米线通道制备了完全兼容CMOS的n-纳米线栅极全能(GAA) n-和p-MOS晶体管，并在低至5K的不同温度下进行了表征。SiNW宽度控制在1nm的步骤和变化从3到6nm。器件具有高驱动电流(n-FET为2.4 mA/mum, p-FET为1.3 mA/mum)，出色的栅极控制和降低的温度灵敏度。在ids - vg振荡和阈值电压随SiNW直径的位移方面，发现了载流子约束的有力证据。取向的影响也进行了研究

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Ultra-Narrow Silicon Nanowire Gate-All-Around CMOS Devices: Impact of Diameter, Channel-Orientation and Low Temperature on Device Performance

Fully CMOS compatible silicon-nanowire (SiNW) gate-all-around (GAA) n- and p-MOS transistors are fabricated with nanowire channel in different crystal orientations and characterized at various temperatures down to 5K. SiNW width is controlled in 1 nm steps and varied from 3 to 6 nm. Devices show high drive current (2.4 mA/mum for n-FET, 1.3 mA/mum for p-FET), excellent gate control, and reduced sensitivity to temperature. Strong evidences of carrier confinement are noticed in term of Id-Vg oscillations and shift in threshold voltage with SiNW diameter. Orientation impact has been investigated as well

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2006 International Electron Devices Meeting

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