0.5 /spl mu/m SOI CMOS工艺在千兆赫频段的低电压、低功率射频应用潜力

R. Bhatia, S. Jalan, S. Chakraborty, S. Yoon, S. Nuttinck, S. Pinel, D. Nobbe, J. Laskar
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引用次数: 1

摘要

绝缘体上硅(SOI)已成为低功率射频应用的有力竞争者。本文展示了SOI技术在下一代射频前端开发中的潜力。0.5 /spl mu/m SOI技术的能力通过设计和制造工作在1.8 GHz的低电源电压、低功耗VCO来说明。VCO在低至1v的电源电压下工作。调谐范围为14%,相位噪声为-117.5 dBc/Hz,偏移频率为1 MHz,偏离1.77 GHz载波。VCO和缓冲器从1.5 V电源消耗14.7 mW功率。我们还展示了该技术中用于亚谐波混频器的反平行二氧化对(APDP)结构的开发、制造和测量。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Potential of 0.5 /spl mu/m SOI CMOS process towards low voltage, low power RF applications in multigigahertz regime
Silicon on insulator (SOI) has emerged as a strong contender for low power RF applications. This paper demonstrates the potential of SOI technology towards the development of next generation RF front ends. The capabilities of a 0.5 /spl mu/m SOI technology are illustrated by the design and fabrication of a low supply voltage, low power VCO operating at 1.8 GHz. The VCO operates with supply voltage as low as 1 V. The tuning range was measured to be 14% and the measured phase noise was -117.5 dBc/Hz at an offset frequency of 1 MHz from the 1.77 GHz carrier. The VCO and the buffers consume 14.7 mW power from a 1.5 V supply. We also demonstrate the development, fabrication and measurement of anti-parallel dioxide pair (APDP) structures towards subharmonic mixers in this technology.
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