采用金属开槽方法的40纳米CMOS 48-61 GHz LNA,最小NF为3.6 dB

Hao Gao, Kuangyuan Ying, M. Matters-Kammerer, P. Harpe, Q. Ma, A. V. van Roermund, P. Baltus
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引用次数: 42

摘要

本文提出了一种采用40纳米CMOS技术实现的60 GHz ISM频段低噪声放大器。为了降低输入被动结构对噪声的贡献,在传输线上采用了新的金属开槽方法,以增加有效导电截面面积。该设计在共源级和共门级之间加入了额外的噪声匹配,以减少后一级的噪声影响。测得的噪声系数在51 GHz ~ 65 GHz范围内小于4db,在55 GHz范围内小于3.6 dB,在60 GHz范围内小于3.8 dB。实现的3db功率增益带宽为13 GHz,从48 GHz到61 GHz。换能器增益峰值(Gt)在55 GHz时为15 dB,在60 GHz时为12.5 dB。总功耗为20.4 mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A 48–61 GHz LNA in 40-nm CMOS with 3.6 dB minimum NF employing a metal slotting method
This paper presents a low noise amplifier realized in 40-nm CMOS technology for the 60 GHz ISM band. To reduce the noise contribution from the input passive structure, a new metal slotting method is applied to the transmission line for increasing the effective conducting cross-section area. The design incorporates additional noise matching between the common-source stage and the common-gate stage to reduce the noise impact by the latter stage. The measured noise figure is below 4 dB from 51 GHz to 65 GHz, 3.6 dB at 55 GHz and 3.8 dB at 60 GHz. The achieved 3 dB power gain bandwidth is 13 GHz, from 48 GHz to 61 GHz. The peak transducer gain (Gt) is 15 dB at 55 GHz, and 12.5 dB at 60 GHz. The total power consumption is 20.4 mW.
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